cpldfit:  version G.37                              Xilinx Inc.
                                  Fitter Report
Design Name: finalalarm                          Date:  3- 7-2005,  4:32PM
Device Used: XCR3064XL-6-PC44
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
12 /64  ( 19%) 19  /224  (  8%) 2  /64  (  3%) 19 /32  ( 59%) 22 /160 ( 14%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    8           8    |  I/O              :    18       10
Output        :   10          10    |  GCK/IO           :     1        3
Bidirectional :    0           0    |  
GCK           :    1           1    |  
                 ----        ----
        Total      19          19 

MACROCELL RESOURCES:

Total Macrocells Available                    64
Registered Macrocells                          2
Non-registered Macrocell driving I/O          10

GLOBAL RESOURCES:

Signal 'CLKIN' mapped onto global clock net GCK0.
Universal Control Terms (Used/Total)                      : 0/4

BLOCK RESOURCES:

Total Function Block Local Control Terms (Used/Total)     : 0/32
Total Foldback NANDs (Used/Total)                         : 0/32

End of Resource Summary
*************** Summary of Required Resources ******************

** LOGIC **
Signal              Total Signals Loc     Slew Pin  Pin       Pin     Reg Init
Name                Pt    Used            Rate #    Type      Use     State
CATHY               0       0     FB4_9   FAST 18   I/O       O       
DISPOUT<0>          1       2     FB4_12  FAST 21   I/O       O       
DISPOUT<1>          1       3     FB3_13  FAST 24   I/O       O       
DISPOUT<2>          2       3     FB3_12  FAST 25   I/O       O       
DISPOUT<3>          1       3     FB3_11  FAST 26   I/O       O       
DISPOUT<4>          1       2     FB3_10  FAST 27   I/O       O       
DISPOUT<5>          0       0     FB3_9   FAST 28   I/O       O       
DISPOUT<6>          1       3     FB3_4   FAST 29   I/O       O       
XLXI_5/Q1           4       10    FB1_9        38   TDO/I/O   (b)     RESET
XLXI_5/Q2           6       10    FB1_16            (b)       (b)     RESET
alarmOUT            4       10    FB3_2   FAST 31   I/O       O       
armedOUT            2       6     FB1_1   FAST 41   I/O       O       

** INPUTS **
Signal                            Loc          Pin  Pin       Pin      I/O 
Name                                           #    Type      Use     Style
CLKIN                                          2    GCK/I     GCK                
SW5                               FB4_5        17   I/O       I                  
SW6                               FB4_4        16   I/O       I                  
SW7                               FB4_2        14   I/O       I                  
SW8                               FB2_15       12   I/O       I                  
comparatorIN<0>                   FB2_11       9    I/O       I                  
comparatorIN<1>                   FB2_10       8    I/O       I                  
comparatorIN<2>                   FB2_3        6    I/O       I                  
comparatorIN<3>                   FB2_2        5    I/O       I                  

End of Resources

Legend: PU  - Pull Up
*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           3          10          10            9         1/0        7   
FB2           0           0           0            0         0/0        7   
FB3           7          10          10            9         7/0        7   
FB4           2           2           2            1         2/0        7   
            ----                                -----       -----     ----- 
             12                                   19        10/0       28   
*********************************** FB1 ***********************************
Number of signals used by logic mapping into function block:  10
Number of function block inputs used/remaining:               10/30
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   9/39
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
armedOUT                            2    FB1_1      41   I/O     O
(unused)                            0    FB1_2      40   I/O      
(unused)                            0    FB1_3           (b)      
(unused)                            0    FB1_4           (b)      
(unused)                            0    FB1_5           (b)      
(unused)                            0    FB1_6           (b)      
(unused)                            0    FB1_7           (b)      
(unused)                            0    FB1_8      39   I/O      
XLXI_5/Q1                           4    FB1_9      38TDO/I/O   (b)
(unused)                            0    FB1_10     37   I/O      
(unused)                            0    FB1_11     36   I/O      
(unused)                            0    FB1_12          (b)      
(unused)                            0    FB1_13          (b)      
(unused)                            0    FB1_14     34   I/O      
(unused)                            0    FB1_15     33   I/O      
XLXI_5/Q2                           6    FB1_16          (b)   (b)

Signals Used by Logic in Function Block
  1: SW5                5: XLXI_5/Q1          8: comparatorIN<1> 
  2: SW6                6: XLXI_5/Q2          9: comparatorIN<2> 
  3: SW7                7: comparatorIN<0>   10: comparatorIN<3> 
  4: SW8              

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
armedOUT          ....XXXXXX.............................. 6       6
XLXI_5/Q1         XXXXXXXXXX.............................. 10      10
XLXI_5/Q2         XXXXXXXXXX.............................. 10      10
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB2 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB2_1       4   I/O      
(unused)                            0    FB2_2       5   I/O     I
(unused)                            0    FB2_3       6   I/O     I
(unused)                            0    FB2_4           (b)      
(unused)                            0    FB2_5           (b)      
(unused)                            0    FB2_6           (b)      
(unused)                            0    FB2_7           (b)      
(unused)                            0    FB2_8           (b)      
(unused)                            0    FB2_9       7TDI/I/O      
(unused)                            0    FB2_10      8   I/O     I
(unused)                            0    FB2_11      9   I/O     I
(unused)                            0    FB2_12          (b)      
(unused)                            0    FB2_13          (b)      
(unused)                            0    FB2_14     11   I/O      
(unused)                            0    FB2_15     12   I/O     I
(unused)                            0    FB2_16          (b)      
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB3 ***********************************
Number of signals used by logic mapping into function block:  10
Number of function block inputs used/remaining:               10/30
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   9/39
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB3_1      32TCK/I/O      
alarmOUT                            4    FB3_2      31   I/O     O
(unused)                            0    FB3_3           (b)      
DISPOUT<6>                          1    FB3_4      29   I/O     O
(unused)                            0    FB3_5           (b)      
(unused)                            0    FB3_6           (b)      
(unused)                            0    FB3_7           (b)      
(unused)                            0    FB3_8           (b)      
DISPOUT<5>                          0    FB3_9      28   I/O     O
DISPOUT<4>                          1    FB3_10     27   I/O     O
DISPOUT<3>                          1    FB3_11     26   I/O     O
DISPOUT<2>                          2    FB3_12     25   I/O     O
DISPOUT<1>                          1    FB3_13     24   I/O     O
(unused)                            0    FB3_14          (b)      
(unused)                            0    FB3_15          (b)      
(unused)                            0    FB3_16          (b)      

Signals Used by Logic in Function Block
  1: SW5                5: XLXI_5/Q1          8: comparatorIN<1> 
  2: SW6                6: XLXI_5/Q2          9: comparatorIN<2> 
  3: SW7                7: comparatorIN<0>   10: comparatorIN<3> 
  4: SW8              

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
alarmOUT          XXXXXXXXXX.............................. 10      10
DISPOUT<6>        XXX..................................... 3       3
DISPOUT<5>        ........................................ 0       0
DISPOUT<4>        XX...................................... 2       2
DISPOUT<3>        XXX..................................... 3       3
DISPOUT<2>        XXX..................................... 3       3
DISPOUT<1>        XXX..................................... 3       3
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB4 ***********************************
Number of signals used by logic mapping into function block:  2
Number of function block inputs used/remaining:               2/38
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   1/47
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB4_1      13TMS/I/O      
(unused)                            0    FB4_2      14   I/O     I
(unused)                            0    FB4_3           (b)      
(unused)                            0    FB4_4      16   I/O     I
(unused)                            0    FB4_5      17   I/O     I
(unused)                            0    FB4_6           (b)      
(unused)                            0    FB4_7           (b)      
(unused)                            0    FB4_8           (b)      
CATHY                               0    FB4_9      18   I/O     O
(unused)                            0    FB4_10     19   I/O      
(unused)                            0    FB4_11     20   I/O      
DISPOUT<0>                          1    FB4_12     21   I/O     O
(unused)                            0    FB4_13          (b)      
(unused)                            0    FB4_14          (b)      
(unused)                            0    FB4_15          (b)      
(unused)                            0    FB4_16          (b)      

Signals Used by Logic in Function Block
  1: SW5                2: SW6              

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
CATHY             ........................................ 0       0
DISPOUT<0>        XX...................................... 2       2
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
;;-----------------------------------------------------------------;;
; Implemented Equations.


CATHY <= '1';


DISPOUT(0) <= NOT ((NOT SW6 AND NOT SW5));


DISPOUT(1) <= (NOT SW6 AND NOT SW5 AND NOT SW7);


DISPOUT(2) <= ((SW6 AND NOT SW5)
	OR (NOT SW5 AND NOT SW7));


DISPOUT(3) <= NOT ((NOT SW6 AND NOT SW5 AND SW7));


DISPOUT(4) <= NOT ((SW6 AND NOT SW5));


DISPOUT(5) <= '1';


DISPOUT(6) <= NOT ((NOT SW6 AND NOT SW5 AND SW7));


alarmOUT <= NOT (((XLXI_5/Q2 AND XLXI_5/Q1)
	OR (NOT XLXI_5/Q2 AND NOT XLXI_5/Q1)
	OR (comparatorIN(2) AND comparatorIN(1) AND 
	comparatorIN(3) AND NOT comparatorIN(0))
	OR (NOT SW6 AND NOT SW5 AND NOT SW7 AND NOT SW8 AND XLXI_5/Q2)));

FDCPE_XLXI_5/Q2: FDCPE port map (XLXI_5/Q2,XLXI_5/Q2_D,CLKIN,'0','0','1');
XLXI_5/Q2_D <= NOT (((XLXI_5/Q1)
	OR (SW6 AND XLXI_5/Q2)
	OR (SW5 AND XLXI_5/Q2)
	OR (SW7 AND XLXI_5/Q2)
	OR (SW8 AND XLXI_5/Q2)
	OR (comparatorIN(2) AND comparatorIN(1) AND 
	comparatorIN(3) AND NOT comparatorIN(0))));

FDCPE_XLXI_5/Q1: FDCPE port map (XLXI_5/Q1,XLXI_5/Q1_D,CLKIN,'0','0','1');
XLXI_5/Q1_D <= NOT (((XLXI_5/Q2 AND XLXI_5/Q1)
	OR (NOT XLXI_5/Q2 AND NOT XLXI_5/Q1)
	OR (comparatorIN(2) AND comparatorIN(1) AND 
	comparatorIN(3) AND NOT comparatorIN(0))
	OR (NOT SW6 AND NOT SW5 AND NOT SW7 AND NOT SW8 AND XLXI_5/Q2)));


armedOUT <= NOT (((XLXI_5/Q2 AND XLXI_5/Q1)
	OR (comparatorIN(2) AND comparatorIN(1) AND 
	comparatorIN(3) AND NOT comparatorIN(0))));


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

****************************  Device Pin Out ****************************

Device : XCR3064XL-6-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11       XCR3064XL-6-PC44     35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 TIE                              23 VCC                           
  2 CLKIN                            24 DISPOUT<1>                    
  3 VCC                              25 DISPOUT<2>                    
  4 WPU                              26 DISPOUT<3>                    
  5 comparatorIN<3>                  27 DISPOUT<4>                    
  6 comparatorIN<2>                  28 DISPOUT<5>                    
  7 TDI                              29 DISPOUT<6>                    
  8 comparatorIN<1>                  30 GND                           
  9 comparatorIN<0>                  31 alarmOUT                      
 10 PE                               32 TCK                           
 11 WPU                              33 WPU                           
 12 SW8                              34 WPU                           
 13 TMS                              35 VCC                           
 14 SW7                              36 WPU                           
 15 VCC                              37 WPU                           
 16 SW6                              38 TDO                           
 17 SW5                              39 WPU                           
 18 CATHY                            40 WPU                           
 19 WPU                              41 armedOUT                      
 20 WPU                              42 GND                           
 21 DISPOUT<0>                       43 TIE                           
 22 GND                              44 TIE                           


Legend :  NC  = Not Connected, unbonded pin
          PE  = Port Enable pin
         WPU  = Unused with Internal Weak Pull Up
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xcr3064xl-6-PC44
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : PULLUP
Set Input-Only Termination                  : FLOAT
Set Universal Control Term Optimization     : OFF
Enable Foldback NANDs                       : OFF
Reserve ISP Pins                            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Input Limit                                 : 32
Pterm Limit                                 : 28