CATHY <= '1'; |
DISPOUT(0) <= NOT ((NOT SW6 AND NOT SW5)); |
DISPOUT(1) <= (NOT SW6 AND NOT SW5 AND NOT SW7); |
DISPOUT(2) <= ((SW6 AND NOT SW5) OR (NOT SW5 AND NOT SW7)); |
DISPOUT(3) <= NOT ((NOT SW6 AND NOT SW5 AND SW7)); |
DISPOUT(4) <= NOT ((SW6 AND NOT SW5)); |
DISPOUT(5) <= '1'; |
DISPOUT(6) <= NOT ((NOT SW6 AND NOT SW5 AND SW7)); |
alarmOUT <= NOT (((XLXI_5/Q2 AND XLXI_5/Q1) OR (NOT XLXI_5/Q2 AND NOT XLXI_5/Q1) OR (comparatorIN(2) AND comparatorIN(1) AND comparatorIN(3) AND NOT comparatorIN(0)) OR (NOT SW6 AND NOT SW5 AND NOT SW7 AND NOT SW8 AND XLXI_5/Q2))); |
FDCPE_XLXI_5/Q2: FDCPE port map (XLXI_5/Q2,XLXI_5/Q2_D,CLKIN,'0','0','1'); XLXI_5/Q2_D <= NOT (((XLXI_5/Q1) OR (SW6 AND XLXI_5/Q2) OR (SW5 AND XLXI_5/Q2) OR (SW7 AND XLXI_5/Q2) OR (SW8 AND XLXI_5/Q2) OR (comparatorIN(2) AND comparatorIN(1) AND comparatorIN(3) AND NOT comparatorIN(0)))); |
FDCPE_XLXI_5/Q1: FDCPE port map (XLXI_5/Q1,XLXI_5/Q1_D,CLKIN,'0','0','1'); XLXI_5/Q1_D <= NOT (((XLXI_5/Q2 AND XLXI_5/Q1) OR (NOT XLXI_5/Q2 AND NOT XLXI_5/Q1) OR (comparatorIN(2) AND comparatorIN(1) AND comparatorIN(3) AND NOT comparatorIN(0)) OR (NOT SW6 AND NOT SW5 AND NOT SW7 AND NOT SW8 AND XLXI_5/Q2))); |
armedOUT <= NOT (((XLXI_5/Q2 AND XLXI_5/Q1) OR (comparatorIN(2) AND comparatorIN(1) AND comparatorIN(3) AND NOT comparatorIN(0)))); |
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |